搜索资源列表
leon3-altera-ep2s60-sdr
- ahb sdram interface.arm cpu series,include controller
ahb_system_generator.tar
- An AHB system is made of masters slaves and interconnections. A general approach to include all possible \"muxed\" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a mas
CorePCIF_AHB_hb
- AHB to PCI Structure for FPGA/Asic Designer
SLAVERAM
- AHB slave 的一个简单的原型程序，通过参考该程序，可以写出相应的ahb slave 代码
ARM_SPI
- arm spi寄存器的使用方法实例，各种初始化寄存器使用方法等-arm spi register to use examples
LIP1201CORE_dll
- Verilog DLL sOURCE CODE
simulator
- 开源的基于SystemC的模拟器，可以模拟ARM CPU, Cache, DDR，NOR, NAND, 时序和功耗均可以正确模拟。-This simulator is a cycle-accurate system-level energy and timing simulator. Developed by Embedded Low-Power Laboratory, Seoul National University. The simulator’s underlying kernel is
ahbapb
- AMBA2.0标准的AHB2APb桥，代码通过验证-AMBA2.0 standard AHB2APb Bridge, through the verification code
ahb_arbiter
- USB v1.1 RTL and design specification
AMBA
- 基于AMBA总线的DDR2 SDRAM控制器研究与实现-AMBA bus-based Research and Implementation of DDR2 SDRAM Controller
ahb2wishbone_latest.tar
- AHB总线到wishbone总线的转化的Verilog源码-AHB to wishbone verilog source code
pxa_27x_dev_man
- SOC ARM AMBA AHB-Lite 多层总线设计 PX310-P310 platform
usb_drv
- USB驱动代码,-C--源码，很有参考价值。值得学习-USB DRIVE
ahblitemaster
- ahb master for single state representation code
SysTick
- This example shows how to configure the SysTick to generate a time base equal to 1 ms. The system clock is set to 72 MHz, the SysTick is clocked by the AHB clock (HCLK).
DVI0045B_multilayer_ahb_overview
- This is multilayer view of amba ahb
AMBA
- AHB SPECIFICATION SPECIFICATION SPECIFICATION SPECIFICATION-AHB SPEC YOU KNOW IT THAT IS RIGHT, SPECIFICATION SPECIFICATION SPECIFICATION SPECIFICATION SPECIFICATION
dma_ahb_latest.tar
- AHB DMA verilog源码 AHB总线 DMA接口源码(AHB bus DMA interface source code)
AHB2-master
- verilog ahb master and slave